![]() If s 3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I 15 to I 8 based on the values of selection lines s 2, s 1 & s 0. If s 3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is 7 to I 0 based on the values of selection lines s 2, s 1 & s 0. The other selection line, s 3 is applied to 2x1 Multiplexer. The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. Therefore, each 8x1 Multiplexer produces an output based on the values of selection lines, s 2, s 1 & s 0. The data inputs of upper 8x1 Multiplexer are I 15 to I 8 and the data inputs of lower 8x1 Multiplexer are I 7 to I 0. The same selection lines, s 2, s 1 & s 0 are applied to both 8x1 Multiplexers. The block diagram of 16x1 Multiplexer is shown in the following figure. We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The Truth table of 16x1 Multiplexer is shown below. Let the 16x1 Multiplexer has sixteen data inputs I 15 to I 0, four selection lines s 3 to s 0 and one output Y. Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output. So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines and one output. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as one 8x1 Multiplexer. If s 2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to I 4 based on the values of selection lines s 1 & s 0. If s 2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 3 to I 0 based on the values of selection lines s 1 & s 0. The other selection line, s 2 is applied to 2x1 Multiplexer. The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines, s 1 & s 0. The data inputs of upper 4x1 Multiplexer are I 7 to I 4 and the data inputs of lower 4x1 Multiplexer are I 3 to I 0. The same selection lines, s 1 & s 0 are applied to both 4x1 Multiplexers. The block diagram of 8x1 Multiplexer is shown in the following figure. We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The Truth table of 8x1 Multiplexer is shown below. Let the 8x1 Multiplexer has eight data inputs I 7 to I 0, three selection lines s 2, s 1 & s0 and one output Y. Since, each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output. ![]() So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers. Implementation of Higher-order Multiplexers. Similarly, you can implement 8x1 Multiplexer and 16x1 multiplexer by following the same procedure. We can easily understand the operation of the above circuit. The circuit diagram of 4x1 multiplexer is shown in the following figure. We can implement this Boolean function using Inverters, AND gates & OR gate. ![]() Selection Linesįrom Truth table, we can directly write the Boolean function for output, Y as Truth table of 4x1 Multiplexer is shown below. One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. The block diagram of 4x1 Multiplexer is shown in the following figure. 4x1 MultiplexerĤx1 Multiplexer has four data inputs I 3, I 2, I 1 & I 0, two selection lines s 1 & s 0 and one output Y. So, each combination will select only one data input. Since there are ‘n’ selection lines, there will be 2 n possible combinations of zeros and ones. ![]() One of these data inputs will be connected to the output based on the values of selection lines. Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines and single output line. ![]()
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